Many networks transmit clocked data without the corresponding clock signal to decrease noise and increase the bandwidth of the interconnection medium, or data transmission medium. Even when transmitting clocked data across a transmission medium without the corresponding clock signals, noise in the data signal, such as transmitter jitter, channel jitter and data dependent jitter, reduces the sampling window for data. For example, transmitter jitter can result from many sources such as feed through, random jitter, systematic offsets and duty cycle distortion. Duty cycle distortion, for instance, is caused by non-symmetric positive and negative duty cycles of a data symbol and can show up either as a high frequency correlated jitter or as a phase step. Further, channel jitter can result from phase dispersion, such as inter-symbol interference (ISI). When a long stream of ones, primarily a sinusoid of 8 MHz and 24 MHz, transitions into a long stream of zeros, primarily a sinusoid of 16 MHz, differences in the propagation delay between 8 MHz, 16 MHz, and 24 MHz of the transmission medium can cause phase shifts at each transition point. The phase shifts, phase steps, and reduced duty cycles reduce the perceivable sampling window by the receiver.
Receivers are designed to compensate for the smaller sampling window by attempting to align the data sampling clock signal, or recovered clock signal, with the center of the data-sampling window. Receivers incorporate a clock generator such as a voltage-controlled oscillator (VCO) with a phase-locked loop (PLL) to follow the phase of the data signal to align data samples with the center of a sampling window. Further, in many applications, the data is re-transmitted at a second clock frequency, usually near the frequency of the data signal. For instance, in synchronous optical networks (SONET), an optical carrier (OC) is received, converted into electrical signals, amplified, and deserialized by serializer-deserializer circuitry. However, using two VCO's on a chip to sample and re-transmit the data of the data signal can result in the noise coupling, typically called injection locking. Injection locking describes noise coupling between two VCO's through their power supplies, ground lines, or substrate, that locks the phases of the two VCO's for a short time when their phases cross.
Serializer-deserializer circuitry is designed to avoid or attenuate the effects of injection locking. Some serializer-deserializer circuitry is provided in two separate chips, a receiver chip with a data sampling VCO and a transmitter chip with a transmission VCO. The receive and transmit chips are matched to optimize performance but take more physical space in a layout and increase production and distribution costs for the serializer-deserializer circuitry. Other serializer-deserializer circuitry attempts to avoid the effects of injection locking while maintaining the receiver circuitry and transmitter circuitry on the same chip by incorporating a VCO that outputs more than one phase of a clock signal and selecting the receive and re-transmit clock signals from the VCO or from a discrete number of interpolated phase steps between the phases of the VCO. The discrete steps result from digital control of changes made to the phase of the interpolated clock signal, referred to as a recovered clock signal in these applications. The discrete phase steps present a problem, however, since the steps feasibly obtained from a VCO are large with respect to the phase shifts resulting from noise, especially with respect to data signals in the gigahertz range, and result in significant differential non-linearities in the interpolated clock signal when transitioning between phases.